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FDM3622 N-Channel PowerTrench(R) MOSFET
January 2005
FDM3622 N-Channel PowerTrench(R) MOSFET
100V, 4.4A, 60m Features
r DS(ON) = 44m (Typ.), VGS = 10V, ID = 4.4A Qg(tot) = 13nC (Typ.), VGS = 10V Low Miller Charge Low QRR Body Diode Optimized efficiency at high frequencies UIS Capability (Single Pulse and Repetitive Pulse)
General Description
This N-Channel MOSFET is produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance.
Applications
Distributed Power Architectures and VRMs Primary Switch for 24V and 48V Systems High Voltage Synchronous Rectifier Formerly developmental type 82744
1 2 3 4
8 7 6 5
MicroFET 3.3 x 3.3
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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FDM3622 N-Channel PowerTrench(R) MOSFET
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC = 25 oC, VGS = 10V, RJA = 52oC/W) Continuous (TC = 25 C, VGS = 6V, RJA = 52 C/W) Continuous (TC = 100oC, VGS = 10V, RJA = 52oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 2) Power dissipation Derate above 25oC Operating and Storage Temperature
o o
Ratings 100 20 4.4 3.8 2.8 Figure 4 190 2.4 19 -55 to 150
Units V V A A A mJ W mW/oC
o
C
Thermal Characteristics
RJA RJA RJC Thermal Resistance Junction to Ambient (Note 1a) Thermal Resistance Junction to Ambient (Note 1b) Thermal Resistance Junction to Case (Note 1) 52 108 1.8
oC/W o o
C/W C/W
Package Marking and Ordering Information
Device Marking FDM3622 Device FDM3622 Package MicroFET3.3x3.3 Reel Size 7" Tape Width 12mm Quantity 3000 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
B VDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 80V VGS = 0V VGS = 20V TC = 100oC 100 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage V GS = VDS, ID = 250A ID = 4.4A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 3.8A, VGS = 6V, ID = 4.4A, VGS = 10V, TC = 150oC 2 0.044 0.056 0.092 4 0.060 0.080 0.120 V
Dynamic Characteristics
CISS COSS CRSS RG Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0.5V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 50V ID = 4.4A Ig = 1.0mA 820 125 35 3.1 13 1.6 3.6 2.0 3.4 17 2.1 pF pF pF nC nC nC nC nC
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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FDM3622 N-Channel PowerTrench(R) MOSFET
Resistive Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 50V, ID = 4.4A VGS = 10V, RGS = 24 11 25 35 26 54 92 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR
Notes: 1. RJA is determined with the device mounted on a 1in2 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RJC is guaranteed by design while R JA is determined by the user's board design. (a). RJA = 52C/W when mounted on a 1in2 pad of 2 oz. copper. (b). RJA = 108C/W when mounted on a minimum pad of 2 oz. copper 2. Starting TJ = 25C, L = 31mH, I AS = 3.5A, VDD = 100V
Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge
ISD = 4.4A ISD = 2.2A ISD = 4.4A, dISD/dt = 100A/s ISD = 4.4A, dISD/dt = 100A/s
-
-
1.25 1.0 56 108
V V ns nC
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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FDM3622 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TC = 25C unless otherwise noted
1.2 6
POWER DISSIPATION MULTIPLIER
1.0 ID, DRAIN CURRENT (A) VGS = 10V 4
0.8
0.6
0.4
2
0.2 0 0 25 50 75 100 125 150 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (o C) TA, AMBIENT TEMPERATURE (oC)
0
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 ZJA, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Ambient Temperature
0.1
PDM
t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 102 103
0.01 10-5 10 -4 10-3 10-2 t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
200 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
100 IDM, PEAK CURRENT (A)
VGS = 10V
10
3 10-5 10-4 10-3 10-2 10-1 t , PULSE WIDTH (s) 100 101 102 103
Figure 4. Peak Current Capability
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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FDM3622 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TC = 25C unless otherwise noted
100 20 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100s 10
10
STARTING TJ = 25oC
1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TA = 25oC
1ms
10ms
STARTING TJ = 150 oC 1
0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 120
0.001
0.01
0.1
1
10
100
tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
10
10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
VGS = 10V 8
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25o C VGS = 5V
ID , DRAIN CURRENT (A)
8
6 TJ = 150oC 4 TJ = 25oC 2 TJ = -55 oC
6
4
VGS = 4.7V
VGS = 4.5V 2
0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VGS , GATE TO SOURCE VOLTAGE (V)
0 0 0.5 1.0 1.5 2.0 2.5 3.0 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
80 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 70 ID = 4.4A 60 ID = 0.2A 50
Figure 8. Saturation Characteristics
2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0
1.5
1.0
0.5 VGS = 10V, ID = 4.4A
40 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V)
0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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FDM3622 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TC = 25C unless otherwise noted
1.2 VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 ID = 250A
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
1200
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 50V 8
1000 CISS = CGS + C GD C, CAPACITANCE (pF) COSS CDS + CGD
6
100
CRSS = CGD
4
2
VGS = 0V, f = 1MHz 10 0.1 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 0 3 6
WAVEFORMS IN DESCENDING ORDER: ID = 4.4A ID = 1A 9 12 15
Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Currents
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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FDM3622 N-Channel PowerTrench(R) MOSFET
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD
+
BVDSS
VDS
VDD
IAS 0.01
0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT) VDS
L VGS = 10V VGS
+
VDD DUT Ig(REF) 0 Qg(TH)
VGS VGS = 2V Qgs2 Qgs Ig(REF) 0 Qgd
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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FDM3622 N-Channel PowerTrench(R) MOSFET
PSPICE Electrical Model
.SUBCKT FDM3622 2 1 3 ; Ca 12 8 2.5e-10 Cb 15 14 2.5e-10 Cin 6 8 8e-10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 109 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 1.06e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 0.19e-9 RLgate 1 9 10.6 RLdrain 2 5 10 RLsource 3 7 1.9 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 9e-3 Rgate 9 20 3.16 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 27.7e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),2.5))} .MODEL DbodyMOD D (IS=1.2E-12 RS=9.4e-3 TRS1=2.0e-3 TRS2=4.5e-7 + CJO=5.5e-10 M=0.56 TT=4.4e-8 XTI=4.0) .MODEL DbreakMOD D (RS=0.6 TRS1=1.4e-3 TRS2=-5e-5) .MODEL DplcapMOD D (CJO=2.0e-10 IS=1.0e-30 N=10 M=0.54) .MODEL MmedMOD NMOS (VTO=3.58 KP=2.8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.16) .MODEL MstroMOD NMOS (VTO=4.26 KP=32 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.12 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=31.6 RS=0.1) .MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-1.1e-8) .MODEL RdrainMOD RES (TC1=3.0e-2 TC2=5e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.9e-6) .MODEL RsourceMOD RES (TC1=1.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-3.4e-3 TC2=1.8e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.0 VOFF=-2.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-6.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
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GATE 1 RLGATE CIN
rev October 2004
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 7 RLSOURCE SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
(c)2005 Fairchild Semiconductor Corporation FDM3622 Rev. A
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+
DBODY
FDM3622 N-Channel PowerTrench(R) MOSFET
SABER Electrical Model
REV October 2004 ttemplate FDM3622 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.2e-12,rs=9.4e-3,trs1=2.0e-3,trs2=4.5e-7,cjo=5.5e-10,m=0.56,tt=4.4e-8,xti=4.0) dp..model dbreakmod = (rs=0.6,trs1=1.4e-3,trs2=-5.0e-5) dp..model dplcapmod = (cjo=2.0e-10,isl=10.0e-30,nl=10,m=0.54) m..model mmedmod = (type=_n,vto=3.58,kp=2.8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.26,kp=32,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.12,kp=0.04,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-2.0) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-6.0) DPLCAP 5 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5) c.ca n12 n8 = 2.5e-10 RSLC1 51 c.cb n15 n14 = 2.5e-10 RSLC2 c.cin n6 n8 = 8e-9
ISCL
LDRAIN DRAIN 2 RLDRAIN
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 109 spe.eds n14 n8 n5 n8 = 1 GATE spe.egs n13 n8 n6 n8 = 1 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 1.06e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 0.19e-9 res.rlgate n1 n9 = 10.6 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.9
CA LGATE
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18 -
RLGATE CIN
MSTRO 8
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 12 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK
18 RVTEMP 19 VBAT + 22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-1.1e-8 res.rdrain n50 n16 = 9e-3, tc1=3.0e-2,tc2=5e-5 res.rgate n9 n20 = 3.16 res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=2.9e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 27.7e-3, tc1=1.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-3.4e-3,tc2=1.8e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 2.5)) } }
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FDM3622 N-Channel PowerTrench(R) MOSFET
SPICE Thermal Model
REV October 2004 FDM3622_JA Junction Ambient Copper Area = 1sq.in CTHERM1 TH c2 1.1e-4 CTHERM2 c2 c3 1.2e-4 CTHERM3 c3 c4 3.0e-4 CTHERM4 c4 c5 2.0e-3 CTHERM5 c5 c6 6.4e-3 CTHERM6 c6 c7 3.2e-2 CTHERM7 c7 c8 2.9e-1 CTHERM8 c8 Ambient 3 RTHERM1 TH c2 2.0e-2 RTHERM2 c2 c3 1.3e-1 RTHERM3 c3 c4 2.0e-1 RTHERM4 c4 c5 1.1 RTHERM5 c5 c6 3.3 RTHERM6 c6 c7 6.8 RTHERM7 c7 c8 12.2 RTHERM8 c8 Ambient 27
RTHERM1 2 CTHERM1 th JUNCTION
RTHERM2 3
CTHERM2
RTHERM3 4
CTHERM3
RTHERM4
CTHERM4 5
SABER Thermal Model
SABER thermal model FDM3622 Copper Area = 1sq.in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 =1.1e-4 ctherm.ctherm2 c2 c3 =1.2e-4 ctherm.ctherm3 c3 c4 =3.0e-4 ctherm.ctherm4 c4 c5 =2.0e-3 ctherm.ctherm5 c5 c6 =6.4e-3 ctherm.ctherm6 c6 c7 =3.2e-2 ctherm.ctherm7 c7 c8 =2.9e-1 ctherm.ctherm8 c8 tl =3 rrtherm.rtherm1 th c2 =2.0e-2 rtherm.rtherm2 c2 c3 =1.3e-1 rtherm.rtherm3 c3 c4 =2.0e-1 rtherm.rtherm4 c4 c5 =1.1 rtherm.rtherm5 c5 c6 =3.3 rtherm.rtherm6 c6 c7 =6.8 rtherm.rtherm7 c7 c8 =12.2 rtherm.rtherm8 c8 tl =27 }
RTHERM5 6 CTHERM5
RTHERM6 7
CTHERM6
RTHERM7 8
CTHERM7
RTHERM8
CTHERM8
tl
AMBIENT
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FDM3622 N-Channel PowerTrench(R) MOSFET
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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
11 FDM3622 Rev. A
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